DS3232MZ+【PDF 7/23 页】IC RTC W/SRAM I2C 8SOIC

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DS3232M

±5ppm, I2C Real-Time Clock with SRAM

Maxim Integrated

Control Register (0Eh)

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

EOSC

BBSQW

CONV

INTCN

A2IE

A1IE

BIT 7

EOSC: Enable oscillator. When set to logic 0, the oscillator is started. When set to logic 1, the oscillator is

stopped when the device switches to VBAT. This bit is clear (logic 0) when power is first applied. When the

device is powered by VCC, the oscillator is always on regardless of the status of the EOSC bit. When the oscil-

lator is disabled, all register data is static.

BIT 6

BBSQW: Battery-backed square-wave enable. When set to logic 1 with INTCN = 0 and VCC < VPF, this bit

enables the 1Hz square wave. When BBSQW is logic 0, INT/SQW goes high impedance when VCC falls below

VPF. This bit is disabled (logic 0) when power is first applied.

BIT 5

CONV: Convert temperature. Setting this bit to 1 forces the temperature sensor to convert the temperature

into digital code and execute the temperature compensate algorithm to update the oscillator’s accuracy. The

device cannot be forced to execute the temperature-compensate algorithm faster than once per second. A

user-initiated temperature conversion does not affect the internal update cycle. The CONV bit remains at a 1

from the time it is written until the temperature conversion is completed, at which time both CONV and BSY go

to 0. The CONV bit should be used when monitoring the status of a user-initiated conversion. See Figure 7 for

more details.

BITS 4:3

NA: Not applicable. These bits have no affect on the device and can be set to either 0 or 1.

BIT 2

INTCN: Interrupt control. This bit controls the INT/SQW output signal. When the INTCN bit is set to logic 0, a

1Hz square wave is output on INT/SQW. When the INTCN bit is set to logic 1, a match between the timekeep-

ing registers and either of the alarm registers activates the INT/SQW output (if the alarm is also enabled). The

corresponding alarm flag is always set regardless of the state of the INTCN bit. The INTCN bit is set to a logic

1 when power is first applied.

BIT 1

A2IE: Alarm 2 interrupt enable. When set to logic 1, this bit permits the alarm 2 flag (A2F) bit in the status reg-

ister to assert INT/SQW (when INTCN = 1). When the A2IE bit is set to logic 0 or INTCN is set to logic 0, the

A2F bit does not initiate an interrupt signal. The A2IE bit is disabled (logic 0) when power is first applied.

BIT 0

A1IE: Alarm 1 interrupt enable. When set to logic 1, this bit permits the alarm 1 flag (A1F) bit in the status reg-

ister to assert INT/SQW (when INTCN = 1). When the A1IE bit is set to logic 0 or INTCN is set to logic 0, the

A1F bit does not initiate an interrupt signal. The A1IE bit is disabled (logic 0) when power is first applied

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